RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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CPU program counter (cpu_pc)

A program counter of a RISC CPU as specified in [WSG+:2011].

Download: cpu_pc_246.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 37 37 857 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines
MCT+MCF 92 145 797 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines
MCT+MCF 37 41 865 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V)
MCT+MCF 38 41 505 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines
MCT+MCF 93 147 609 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines
MCT+MCF 38 45 513 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme
 
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