RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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CPU control unit (cpu_control_unit)

A control unit of a RISC CPU as specified in [WSG+:2011].

Download: cpu_control_unit_244.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 391 1243 40433 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines
MCT+MCF 646 1746 22343 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines
MCT+MCF 290 2588 80142 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V)
MCT+MCF 392 1351 10513 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines
MCT+MCF 647 1842 7463 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines
MCT+MCF 291 2786 20756 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme
 
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