RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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Hierarchical circuit (callif)

A simple hierarchical circuit.

Download: callif_241.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 34 210 1522 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 16 bit
MCT+MCF 66 434 3154 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 32 bit
MCT+MCF 66 273 641 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 16 bit
MCT+MCF 130 561 1313 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 32 bit
MCT+MCF 34 212 1524 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 16 bit
MCT+MCF 66 436 3156 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 32 bit
MCT+MCF 34 210 1522 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 16 bit
MCT+MCF 66 434 3154 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 32 bit
MCT+MCF 66 273 641 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 16 bit
MCT+MCF 130 561 1313 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 32 bit
MCT+MCF 34 212 1524 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 16 bit
MCT+MCF 66 436 3156 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 32 bit
 
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